1. Technical Field
The invention relates to the testing of semiconductor devices. More particularly, the invention relates to having the capability to simultaneous probe of all devices on semiconductor wafers in connection with device testing and burn-in.
2. Description of the Prior Art
In semiconductor device manufacturing, increased device densities, additional throughput, and higher device yields are desirable. Typically, wafer prober cards are used in wafer probers and are stepped across a wafer to test individual devices. As integrated circuits (ICs) become more complex the test times are increasing and so is the-cost of test. To this end, it is therefore advantageous to simultaneously probe all the active product devices on semiconductor wafers at the wafer level in connection with device testing and burn-in. This is particularly true in connection with the fabrication of 200 and 300 mm wafers.
One problem in full wafer-level device testing and burn-in has to do with the thermal coefficient of expansion (TCE) of a test probe relative to that of a silicon wafer.
Another problem with full wafer-level probing of devices for testing and burn-in concerns the redistribution of signals from the device die pad pitch to the land pad array pitches which are presently attainable on printed wiring boards. Currently, it is not possible to build a printed wiring board that could accommodate full wafer-level device testing and burn-in in an economical and quick-turn manner.
A further problem with full wafer-level probing of semiconductor wafers for device testing and burn-in concerns the decoupling of thermal mismatch between the silicon wafer under test and the printed wiring board probe card.
Additionally, there is a problem with regard to compliance to overcome flatness tolerance of the printed wiring board surface.
It would be advantageous to provide a solution that allowed full wafer level probing of semiconductor wafers for purposes of device testing and burn-in while avoiding the various problems attendant with such probing, as described above. The solution can be adapted to allow a few steps across a wafer (two or four) to match the capabilities of testers currently in IC manufacturing lines until full wafer test capacity is put in place.
The invention provides a mosaic decal probe, in which a mosaic of probe chips is assembled as a decal onto a thin membrane that is suspended in a ring which is made of a material that has a TCE matching that of the devices on the wafer under test (silicon or III-V materials). The membrane is mounted on the ring in tension, such as it stays in tension throughout a functional temperature range. In this way, the membrane exhibits a functional TCE matching that of the ring. Each probe chip preferably has spring contacts on both sides. Apertures are cut in the membrane to allow the spring contacts on one side of the membrane to protrude through the membrane and contact the printed wiring board. The spring contacts which contact the printed wiring board are allowed to slide during temperature excursions, thereby decoupling the TCE mismatch between the probe chip and the printed wiring board.
Two preferred embodiments are currently contemplated. A first embodiment of the invention uses a low-count mosaic comprised of a few probe chips, for example four probe chips. The probe chips have the same TCE as the wafer under test, e.g. silicon. In this embodiment, the probe chip is peripherally attached to the membrane.
A second embodiment of the invention provides a high-count mosaic, using a high number of probe chips, for example nine or more probe chips. In this embodiment, the probe chips are smaller and can have a slight TCE difference from that of the test wafer, e.g. silicon. For example, the probe chips may be made out of a ceramic material. This embodiment of the invention uses a center attachment to secure the probe chips to the membrane.